CY7C1440AV33-167BZXC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1440AV33-167BZXC Datasheet PDF : 31 Pages
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1446AV33 (512K × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQG DQG
A
CE2
ADSP ADSC
ADV CE3
A
DQB DQB
B
DQG DQG
BWSC BWSG NC/288M BW
A
BWSB BWSF DQB DQB
C
DQG DQG
BWSH BWSD NC/144M CE1 NC/576M BWSE BWSA DQB
DQB
D
DQG DQG VSS
NC
NC/1G OE
GW NC
VSS
DQB DQB
E
DQPG DQPC VDDQ VDDQ VDD
VDD
VDD
VDDQ VDDQ DQPF DQPB
F
DQC DQC VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF DQF
G
DQC
DQC VDDQ VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC DQC VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF DQF
J
DQC DQC VDDQ VDDQ
VDD
NC
VDD
VDDQ VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH DQH VSS
VSS
VSS
NC
N
DQH DQH VDDQ
VDDQ
VDD
NC
P
DQH DQH VSS
VSS
VSS
ZZ
VSS
VDD
VSS
VSS
VDDQ
VSS
VSS
VDDQ
VSS
DQA
DQA
DQA
DQA
DQA
DQA
R
DQPD DQPH VDDQ VDDQ
VDD
VDD
VDD
VDDQ
VDDQ DQPA DQPE
T
DQD DQD VSS
NC
NC
MODE NC
NC
VSS
DQE DQE
U
DQD DQD NC/72M A
A
V
DQD DQD
A
A
A
W
DQD DQD TMS
TDI
A
A
A
A1
A
A0
A
A
A
DQE DQE
A
A
DQE DQE
TDO
TCK
DQE DQE
Pin Definitions
Name
A0, A1, A
I/O
Input-
Synchronous
BWA, BWB,
BWC, BWD,
BWE, BWF,
BWG, BWH
GW
Input-
Synchronous
Input-
Synchronous
BWE
CLK
CE1
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active.
A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BWX and
BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
sampled only when a new external address is loaded.
Document #: 38-05383 Rev. *E
Page 6 of 31
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