CY7C1440AV33-167BZXC 查看數據表（PDF） - Cypress Semiconductor
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CY7C1440AV33-167BZXC Datasheet PDF : 31 Pages
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Truth Table [2, 3, 4, 5, 6, 7]
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
100
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power Down
None
H X XL X
L
X
X
X L-H Tri-State
Deselect Cycle, Power Down
None
L L XL L
X
X
X
X L-H Tri-State
Deselect Cycle, Power Down
None
L X HL L
X
X
X
X L-H Tri-State
Deselect Cycle, Power Down
None
L L XL H
L
X
X
X L-H Tri-State
Deselect Cycle, Power Down
None
L X HL H
L
X
X
X L-H Tri-State
Sleep Mode, Power Down
None
X X XH X
X
X
X
X X Tri-State
READ Cycle, Begin Burst
External L H L L L
X
X
X
L L-H Q
READ Cycle, Begin Burst
External L H L L L
X
X
X
H L-H Tri-State
WRITE Cycle, Begin Burst
External L H L L H
L
X
L
X L-H D
READ Cycle, Begin Burst
External L H L L H
L
X
H
L L-H Q
READ Cycle, Begin Burst
External L H L L H
L
X
H H L-H Tri-State
READ Cycle, Continue Burst
Next
X X XL H
H
L
H
L L-H Q
READ Cycle, Continue Burst
Next
X X XL H
H
L
H H L-H Tri-State
READ Cycle, Continue Burst
Next
H X XL X
H
L
H
L L-H Q
READ Cycle, Continue Burst
Next
H X XL X
H
L
H H L-H Tri-State
WRITE Cycle, Continue Burst
Next
X X XL H
H
L
L
X L-H D
WRITE Cycle, Continue Burst
Next
H X XL X
H
L
L
X L-H D
READ Cycle, Suspend Burst Current X X X L H
H
H
H
L L-H Q
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05383 Rev. *E
Page 9 of 31
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