CY14B108N(2011) 查看數據表（PDF） - Cypress Semiconductor
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CY14B108N Datasheet PDF : 25 Pages
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CY14B108L
CY14B108N
Pin Definitions
Pin Name I/O Type
Description
A0–A19
A0–A18
DQ0–DQ7
DQ0–DQ15
WE
Input
Input/Output
Input
Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
BHE
BLE
VSS
VCC
HSB
Input
Input
Ground
Byte High Enable, Active LOW. Controls DQ15–DQ8.
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device.
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC
No connect No connect. This pin is not connected to the die.
Document #: 001-45523 Rev. *J
Page 4 of 25
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