74AHC594PW 查看數據表（PDF） - Nexperia B.V. All rights reserved
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74AHC594PW Datasheet PDF : 21 Pages
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Nexperia
74AHC594; 74AHCT594
8-bit shift register with output register
Symbol Parameter Conditions
tW
pulse width SHCP and STCP HIGH or
LOW; see Fig. 9 and Fig. 10
SHR and STR HIGH or LOW;
see Fig. 13 and Fig. 12
tsu
set-up time DS to SHCP; see Fig. 11
SHR to STCP; see Fig. 14
SHCP to STCP; see Fig. 10
th
hold time
DS to SHCP; see Fig. 11
trec
recovery time SHR to SHCP; see Fig. 13
STR to STCP; see Fig. 12
CPD
power
fi = 1 MHz; VI = GND to VCC
dissipation
capacitance
25 °C
Min Typ[1] Max
5.5
-
-
-40 °C to
+85 °C
Min Max
6.0
-
-40 °C to Unit
+125 °C
Min Max
6.5
- ns
5.2
-
-
5.5
-
6.0
- ns
3.0
-
5.0
-
5.0
-
2.0
-
2.9
-
3.4
-
[2] -
55
-
3.0
-
3.5
- ns
-
5.0
-
5.5
- ns
-
5.0
-
5.5
- ns
-
2.0
-
2.5
- ns
-
3.3
-
3.8
- ns
-
3.8
-
4.3
- ns
-
-
-
-
- pF
[1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[2] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC 2 x fo) = sum of the outputs.
11.1. Waveforms
SHCP input
VM
1/fmax
Q7S output
tW
tPLH
VM
tPHL
Fig. 9.
tTLH
tTHL
001aae341
Measurement points are given in Table 8.
Shift register clock pulse width, maximum frequency and input to output propagation delays
74AHC_AHCT594
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 25 June 2020
© Nexperia B.V. 2020. All rights reserved
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