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MPC9772 Datasheet PDF : 17 Pages
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MPC9772 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Power Supply Filtering
The MPC9772 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL power supply impacts the device
characteristics, for instance I/O jitter. The MPC9772 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCC_PLL) of the device. The purpose of
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
VCCA_PLL pin for the MPC9772. Figure 7 illustrates a typical
power supply filter scheme. The MPC9772 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor RF. From the data sheet
the ICC_PLL current (the current sourced through the VCC_PLL
pin) is typically 3 mA (5 mA maximum), assuming that a
minimum of 3.0 V must be maintained on the VCC_PLL pin.
The resistor RF shown in Figure 7 must have a resistance of
5-10 to meet the voltage drop criteria.
RF = 5–10
CF = 22 F
RF
VCC
VCC_PLL
CF
10 nF
MPC9772
VCC
33...100 nF
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9772 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9772. Designs using the MPC9772 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9772 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9772 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9772 are connected together, the maximum overall
timing uncertainty from the common CCLKx input to any
output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
CCLKCommon
–t()
tPD,LINE(FB)
Figure 7. VCC_PLL Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7, the filter cut-off frequency is around
4.5 kHz and the noise attenuation at 100 kHz is better than
42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9772 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Max. skew
tJIT()
+tSK(O)
+t()
tJIT()
+tSK(O)
tSK(PP)
Figure 8. MPC9772 Maximum
Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
MPC9772 REVISION 7 JANUARY 8, 2013
11
©2013 Integrated Device Technology, Inc.
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