MPC9772 查看數據表（PDF） - Integrated Device Technology
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MPC9772 Datasheet PDF : 17 Pages
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MPC9772 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
XTAL_IN
XTAL_OUT
CCLK0
CCLK1
CCLK_SEL
REF_SEL
FB_IN
VCO_SEL
PLL_EN
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
INV_CLK
STOP_DATA
STOP_CLK
MR/OE
All input resistors have a value of 25k
XTAL 1
VCC 0
0
1
Ref
VCO
PLL
VCC
0 4, 6, 8, 12
2 0
1 4, 6, 8, 10
1 1
2, 4, 6, 8
4, 6, 8, 10
12, 16, 20
SYNC PULSE
FB
VCC
2
2
2
3
VCC
Power-On Reset
Clock Stop
12
Figure 1. Logic Diagram
Bank A
CLK
Stop
Bank B
CLK
Stop
Bank C
CLK
Stop
0
CLK
1
Stop
CLK
Stop
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
QFB
QSYNC
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VCC
QA2
GND
QA1
VCC
QA0
GND
VCO_SEL
4039 38 37 36 35 34 33 32 31 30 29 28 2726
41
25
42
24
43
23
44
22
45
21
46
MPC9772
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GND
QC0
VCC
QC1
FSEL_C0
FSEL_C1
QC2
VCC
QC3
GND
INV_CLK
Figure 2. MPC9772 52-Lead Package Pinout (Top View)
MPC9772 REVISION 7 JANUARY 8, 2013
2
©2013 Integrated Device Technology, Inc.
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