DSP56F826PB 查看數據表（PDF） - Motorola => Freescale
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DSP56F826PB Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
Signals and Package Information
Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name
Pin No.
Type
Description
TRST
DE
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7
SRD
(GPIOC0)
4
Input
Test Reset—As an input, a low signal on this pin provides a reset signal
(Schmitt) to the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted whenever RESET is asserted. The only exception
occurs in a debugging environment when a hardware device reset is
required and it is necessary not to reset the JTAG/OnCE module. In this
case, assert RESET, but do not assert TRST. TRST must always be
asserted at power-up.
98
Output
Debug Event—DE provides a low pulse on recognized debug events.
66
Input or
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins
Output
can be individually programmed as input or output pins.
67
After reset, the default state is GPIO input.
68
69
70
71
72
73
74
Input or
Port D GPIO—These eight dedicated GPIO pins can be individually
Output
programmed as an input or output pins.
75
After reset, the default state is GPIO input.
76
77
78
79
82
83
51
Input/Output SSI Receive Data (SRD)—This input pin receives serial data and
transfers the data to the SSI Receive Shift Receiver.
Input/Output Port C GPIO—This is a General Purpose I/O (GPIO) pin with the
capability of being individually programmed as input or output.
After reset, the default state is GPIO input.
56F826 Technical Data
11
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