PE9721 查看數據表（PDF） - Peregrine Semiconductor Corp.

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PE9721

2.7 GHz Integer-N PLL with Field-Programmable EEPROM

Peregrine Semiconductor Corp. 

PE9721

Preliminary Specification

Frequency Registers

There are three independent frequency registers,

any one of which can be selected to control the

operation of the device. Each register is 20 bits in

length, and provides data to the three counters and

the prescaler bypass control. Table 8 defines these

bit assignments.

Primary Register

The Primary Register is a serial shift register,

loaded through the Serial Data Port. It can be

selected to control the PLL as shown in Table 9. It

is not buffered, thus when this register is selected to

control the PLL, its data is continuously presented

to the counters during a load operation.

This register is also used to perform a parallel load

of data into the Secondary Register.

Secondary Register

The Secondary Register is a parallel-load register.

Data is copied into this register from the Primary

Register on the rising edge of S_WR, according to

the timing diagrams shown in Figure 3. It can be

selected to control the PLL as shown in Table 9.

EE Register

The EE Register is a serial/parallel-in,

serial/parallel-out register, and provides the

interface to the EEPROM. It is loaded from the

Serial Data Port to provide the parallel data source

when writing to the EEPROM. It also accepts

stored data from the EEPROM for controlling the

PLL.

Serial loading of the EE Register is done as shown

in Table 7 and Figure 3. Parallel loading of the

register from EEPROM is accomplished as shown

in Table 10.

The EE register can be selected to control the PLL

as shown in Table 9. Note that it cannot be

selected to control the PLL using data that has been

loaded serially. This is because it must first go

through one of the two conditions in Table 10 that

causes the EEPROM data to be copied into the EE

Register. The effect of this is that only EEPROM

data is used when the EE Register is selected.

The contents of the EE register can also be shifted

out serially through the Dout pin. This mode is

enabled by appropriately programming the

Enhancement Register. In this mode, data exits the

register on the rising edge of Clock, LSB (B0) first,

and is replaced with the data present on the Data

input pin. Tables 7 and 12 define the settings

required to enable this mode.

Table 8. Primary / Secondary / EE Register Bit Assignments

R5

R4

M8

M7

PB

M6 M5

M4

M3

M2

M1

M0

R3

R2

R1

R0

A3

A2

A1

A0

B0

B1

B2

B3

B4

B5 B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

Table 9. Frequency Register Selection

EESel

0

0

1

FSel

1

0

X

EELoad

0

0

0

Register Selected

Primary Register

Secondary Register

EE Register

Table 10. EE Register Load from EEPROM

EESel EELoad

Function

_⁄¯

0

EEPROM → EE Register

1

¯\_

EEPROM → EE Register

Copyright  Peregrine Semiconductor Corp. 2003

Page 8 of 13

File No. 70/0098~01B | UTSi  CMOS RFIC SOLUTIONS

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