HMC831LP6CE 查看數據表（PDF） - Analog Devices

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HMC831LP6CE

FRACTIONAL-N PLL WITH INTEGRATED VCO, 1815 - 2010 MHz

Analog Devices 

v05.1211

HMC831LP6CE

FRACTIONAL-N PLL WITH

INTEGRATED VCO, 1815 - 2010 MHz

General Description

The HMC831LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) with an Integrated Voltage Controlled

Oscillator (VCO). The PLL consists of an integrated low noise VCO, an autocalibration subsystem for low voltage VCO

tuning, a very low noise digital Phase Detector (PD), a precision cont-rolled charge pump, a low noise reference path

divider and a fractional divider.

The fractional PLL features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low

spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency

hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency

hopping and low micro-phonics.

For theory of operation and register map refer to the “PLLs with Integrated VCOs - RF VCOs Operating Guide”.

To view the Operating Guide, please visit www.hittite.com and choose HMC831LP6CE from the “Search by Part

Number” pull down menu.

Electrical Specifications, TA = +25° C

VPPCP, VDDCP, VCC1, VCC2 = 5V ±4%; RVDD, AVDD, DVDD3V, VCCPD, VCCHF, VCCPS =

3.3V ±6% GNDCP = GNDLS = Ground Paddle = 0V

Parameter

RF Output Characteristics

VCO Frequency at PLL Input

RF Output Frequency at fVCO

RF Output Power at fVCO

VCO Tuning Sensitivity

VCO Supply Pushing

RF Output 2nd Harmonic

RF Output 3rd Harmonic

RF Output 4th Harmonic

RF Divider Characteristics

19-Bit N-Divider Range (Integer)

19-Bit N-Divider Range (Fractional)

REF Input Characteristics

Max Ref Input Frequency

Ref Input Range

Ref Input Capacitance

14-Bit R-Divider Range

Phase Detector (PD)

PD Frequency Fractional Feedback Mode

PD Frequency Fractional Feedforward Mode

(and Register 6 [17:16] = 10)

PD Frequency Integer Mode

Condition

Internal to the IC Only

Measured at 2 GHz, 2V

Measured at 2 GHz, 2V

Max = 219 - 1

Fractional nominal divide ratio

varies (-3 / +4) dynamically max

Synthesizer phase noise can

degrade by about 5 dB when

operating with a reference

frequency near the low end of

this range.

AC Coupled

[1]

[1]

Min.

1815

1815

4

-2

16

20

10

1.5

1

0.1

0.1

0.1

Typ.

Max.

Units

2010

MHz

2010

MHz

7.5

11

dBm

15

MHz/V

1.5

MHz/V

-25

dBc

-23

dBc

-31

dBc

524,287

524,283

50

200

MHz

2

3.3

Vpp

5

pF

16,383

100

MHz

80

MHz

125

MHz

Note 1: This maximum phase detector frequency can only be achieved if the minimum N value is respected. eg. In the case of fractional feedback

mode, the maximum PFD rate = fvco/20 or 100 MHz, whichever is less.

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