LTC1235CN-TRPBF 查看數據表（PDF） - Linear Technology
零件编号
产品描述 (功能)
生产厂家
LTC1235CN-TRPBF Datasheet PDF : 16 Pages
| |||
LTC1235
Table 1 shows the state of each pin during battery backup.
If the backup battery is not used, connect VBATT to GND
and VOUT to VCC.
Table 1. Input and Output Status in Battery Backup Mode
SIGNAL STATUS
VCC
C2 monitors VCC for active switchover.
BACKUP BACKUP is ignored.
VOUT
VBATT
BATT ON
PFI
PFO
VOUT is connected to VBATT through an internal PMOS switch.
The supply current is 1μA maximum.
Logic high. The open circuit output voltage is equal to VOUT.
Power Failure Input is ignored.
Logic low
PB RST
RESET
PB RST is ignored.
Logic low
RESET Logic high. The open circuit output voltage is equal to VOUT.
LOW LINE Logic low
WDI
WDO
CE IN
CE OUT
Watchdog Input is ignored.
Logic high. The open circuit output voltage is equal to VOUT.
Chip Enable Input is ignored.
Logic high. The open circuit output voltage is equal to VOUT.
Memory Protection
The LTC1235 includes memory protection circuitry which
ensures the integrity of the data in memory by preventing
write operations when VCC is at invalid level. Two pins, CE
IN and CE OUT, control the Chip Enable or Write inputs of
CMOS RAM. When VCC is +5V, CE OUT follows CE IN with
a typical propagation delay of 20ns. When VCC falls below
the reset voltage threshold or VBATT, CE OUT is forced
high, independent of CE IN. CE OUT is an alternative signal
to drive the CE, CS, or Write input of battery-backed up
CMOS RAM. CE OUT can also be used to drive the Store
or Write input of an EEPROM, EAROM or NOVRAM to
achieve similar protection. Figure 6 shows the timing
diagram of CE IN and CE OUT.
CE IN can be derived from the microprocessor’s address
decoder output. Figure 7 shows a typical nonvolatile CMOS
RAM application.
+5V
0.1μF
+3V
VCC
VOUT
LTC1235
CE OUT
VBATT CE IN
BACKUP
GND RESET
+
10μF
0.1μF
20ns PROPAGATION DELAY
FROM DECODER
VCC
62512
RAM
CS
GND
TO μP
1235 F07
Figure 7. A Typical Nonvolatile CMOS RAM Application
BACKUP = VCC
VCC
V2
V1
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CE IN
CE OUT
VOUT = VBATT
Figure 6. Timing Diagram for CE IN and CE OUT
VOUT = VBATT
1235 F06
1235fa
11
Share Link: 