LTC1235CSW-TRPBF 查看數據表（PDF） - Linear Technology

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LTC1235CSW-TRPBF

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

PIN FUNCTIONS

VBATT (Pin 1): Backup battery input. When VCC falls below

VBATT, the status of the BACKUP pin stored in the Memory

Logic controls M2. If the status is high, auxiliary power,

connected to VBATT is delivered to VOUT through M2. If the

status is low, the Memory Logic keeps M2 off and VOUT

is in Battery Saving Mode. If backup battery or auxiliary

power is not used, VBATT should be connected to GND.

VOUT (Pin 2): Voltage output for backed up memory. By-

pass with a capacitor of 0.1μF or greater. During normal

operation, VOUT obtains power from VCC through an NMOS

power switch, M1, which can deliver up to 50mA and has a

typical on resistance of 5Ω. When VCC is lower than VBATT,

the status of the BACKUP pin stored in Memory Logic

controls M2. If the status is high, the Memory Logic turns

on M2 and VOUT is internally switched to VBATT through

M2. If the status is low, the Memory Logic keeps M2 off

and VOUT is in Battery Saving Mode. If VOUT and VBATT

are not used, connect VOUT to VCC.

VCC (Pin 3): +5V supply input. The VCC pin should be

bypassed with a 0.1μF capacitor.

GND (Pin 4): Ground pin.

BATT ON (Pin 5): Battery on logic output from comparator

C2. BATT ON goes low when VOUT is internally connected

to VCC. The output typically sinks 35mA and can provide

base drive for an external PNP transistor to increase the

output current above the 50mA rating of VOUT. BATT ON

goes high when VCC falls below VBATT, if the status of the

BACKUP pin stored in Memory Logic is high and VOUT is

switched to VBATT.

LOW LINE (Pin 6): Logic output from comparator C1.

LOW LINE indicates a low line condition at the VCC input.

When VCC falls below the reset voltage threshold (4.65V

typically), LOW LINE goes low. As soon as VCC rises above

the reset voltage threshold, LOW LINE returns high (see

Figure 1). LOW LINE goes low when VCC drops below VBATT

(see Table 1).

PB RST (Pin 7): Logic input for direct connection to a push-

button. The push-button reset input requires an active low

signal. Internally, this input signal is debounced and timed

for a minimum of 40ms. When this condition is satisfied,

the reset pulse generator forces RESET to active low. The

RESET signal will remain active low for a minimum of 140ms

6

from the moment the push-button reset input is released

from logic low level. Pulled to VCC with 60k.

Backup (Pin 8): Logic input to control the PMOS switch,

M2, when VCC is lower than VBATT. While VCC is falling

through the reset voltage threshold, the status of the

BACKUP pin (logic low or logic high) is latched in Memory

Logic and used to turn on or off M2 when VCC is below

VBATT. If the latched status of the BACKUP pin is high,

the Memory Logic turns on M2 when VCC falls to 50mV

greater than VBATT. If the latched status of the BACKUP

pin is low, the Memory Logic keeps M2 off even after VCC

falls below VBATT. If the BACKUP pin is left floating it will

be pulled high by an internal pullup and the LTC1235 will

provide battery backup when VCC falls.

PFI (Pin 9): Power Failure Input. PFI is the noninverting

input to the Power Fail Comparator, C3. The inverting input

is internally connected to a 1.3V reference. The Power

Failure Output remains high when PFI is above 1.3V and

goes low when PFI is below 1.3V. Connect PFI to GND or

VOUT when C3 is not used.

PFO (Pin 10): Power Failure Output from C3. PFO remains

high when PFI is above 1.3V and goes low when PFI is

below 1.3V. When VCC is lower than VBATT, C3 is shut

down and PFO is forced low.

WDI (Pin 11): Watchdog Input, WDI, is a three level

input. Driving WDI either high or low for longer than the

watchdog time-out period, forces both RESET and WDO

low. Floating WDI disables the Watchdog Timer. The timer

resets itself with each transition of the Watchdog Input

(see Figure 11).

CE OUT (Pin 12): Logic output from the Chip Enable gating

circuit. When VCC is above the reset voltage threshold, CE

OUT is a buffered replica of CE IN. When VCC is below

the reset voltage threshold CE OUT is forced high (see

Figure 6).

CE IN (Pin 13): Logic input to the Chip Enable gating cir-

cuit. CE IN can be derived from microprocessor’s address

line and/or decoder output. See Applications Information

Section and Figure 6 for additional information.

WDO (Pin 14): Watchdog logic output. When the watch-

dog input remains either high or low for longer than the

watchdog time-out period, WDO goes low. WDO is set

1235fa

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