LTC1235CS 查看數據表（PDF） - Linear Technology

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LTC1235CS

Microprocessor Supervisory Circuit

Linear Technology 

LTC1235

PI FU CTIO S

VCC: +5V supply input. The VCC pin should be bypassed

with a 0.1µF capacitor.

Backup: Logic input to control the PMOS switch, M2,

when VCC is lower than VBATT. While VCC is falling through

the reset voltage threshold, the status of the BACKUP pin

(logic low or logic high) is latched in Memory Logic and

used to turn on or off M2 when VCC is below VBATT. If the

latched status of the BACKUP pin is high, the Memory

Logic turns on M2 when VCC falls to 50mV greater than

VBATT. If the latched status of the BACKUP pin is low, the

Memory Logic keeps M2 off even after VCC falls below

VBATT. If the BACKUP pin is left floating it will be pulled high

by an internal pullup and the LTC1235 will provide battery

backup when VCC falls.

VOUT: Voltage output for backed up memory. Bypass with

a capacitor of 0.1µF or greater. During normal operation,

VOUT obtains power from VCC through an NMOS power

switch, M1, which can deliver up to 50mA and has a typical

on resistance of 5Ω. When VCC is lower than VBATT, the

status of the BACKUP pin stored in Memory Logic controls

M2. If the status is high, the Memory Logic turns on M2

and VOUT is internally switched to VBATT through M2. If the

status is low, the Memory Logic keeps M2 off and VOUT is

in Battery Saving Mode. If VOUT and VBATT are not used,

connect VOUT to VCC.

VBATT: Backup battery input. When VCC falls below VBATT,

the status of the BACKUP pin stored in the Memory Logic

controls M2. If the status is high, auxiliary power, connected

to VBATT is delivered to VOUT through M2. If the status is

low, the Memory Logic keeps M2 off and VOUT is in Battery

Saving Mode. If backup battery or auxiliary power is not

used, VBATT should be connected to GND.

GND: Ground pin.

BATT ON: Battery on logic output from comparator C2.

BATT ON goes low when VOUT is internally connected to

VCC. The output typically sinks 35mA and can provide base

drive for an external PNP transistor to increase the output

current above the 50mA rating of VOUT. BATT ON goes

high when VCC falls below VBATT, if the status of the

BACKUP pin stored in Memory Logic is high and VOUT is

switched to VBATT.

PFI: Power Failure Input. PFI is the noninverting input to

the Power Fail Comparator, C3. The inverting input is

internally connected to a 1.3V reference. The Power Failure

Output remains high when PFI is above 1.3V and goes low

when PFI is below 1.3V. Connect PFI to GND or VOUT when

C3 is not used.

PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

1.3V. When VCC is lower than VBATT, C3 is shut down and

PFO is forced low.

PB RST: Logic input for direct connection to a push-

button. The push-button reset input requires an active low

signal. Internally, this input signal is debounced and timed

for a minimum of 40ms. When this condition is satisfied,

the reset pulse generator forces RESET to active low. The

RESET signal will remain active low for a minimum of

140ms from the moment the push-button reset input is

released from logic low level.

RESET: Logic output for µP reset control. The LTC1235

provides three ways to generate µP reset. First, whenever

VCC falls below either the reset voltage threshold (4.65V,

typically) or VBATT, RESET goes active low. After VCC

returns to 5V, the reset pulse generator forces RESET to

remain active low for a minimum of 140ms. Second, when

the watchdog timer is enabled but not serviced prior to the

time-out period, the reset pulse generator also forces

RESET to active low for a minimum of 140ms for every

time-out period (see Figure 11). Third, when the PB RST

pin stays active low for a minimum of 40ms, RESET is

forced low by reset pulse generator. The RESET signal will

remain active low for a minimum of 140ms from the

moment the push-button reset input is released from logic

low level.

RESET: RESET is an active high logic output. It is the

inverse of RESET.

LOW LINE: Logic output from comparator C1. LOW LINE

indicates a low line condition at the VCC input. When VCC

falls below the reset voltage threshold (4.65V typically),

LOW LINE goes low. As soon as VCC rises above the reset

voltage threshold, LOW LINE returns high (see Figure 1).

LOW LINE goes low when VCC drops below VBATT (see

Table 1).

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