W981208AH 查看數據表（PDF） - Winbond

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W981208AH

4M x 8 bit x 4 Banks SDRAM

Winbond 

W981208AH

Pin Assignment

4M x 8 bit x 4 Banks SDRAM

Pin Number Pin Name

23 ~ 26, 22,

29 ~35

A0~ A11

20, 21

BS0, BS1

2, 5, 8, 11,

44, 47, 50, 53

DQ0 ~ DQ7

19

CS#

18

RAS#

17

CAS#

16

WE#

39

DQM

38

CLK

37

CKE

1, 14, 27

28, 41, 54

3, 9, 43, 49

VCC

VSS

VCCQ

6, 12, 46, 52 VSSQ

4, 7, 10, 13,

15, 36, 40, 42, NC

45, 48, 51

Function

Address

Bank Select

Data Input/

Output

Chip Select

Row Address

Strobe

Column Address

Strobe

Write Enable

input/output mask

Clock Inputs

Clock Enable

Power ( +3.3 V )

Ground

Power ( + 3.3 V )

for I/O buffer

Ground for I/O

buffer

No Connection

Description

Multiplexed pins for row and column address.

Row address : A0 ~ A11. Column address: A0 ~ A9.

Select bank to activate during row address latch time, or bank

to read/write during address latch time.

Multiplexed pins for data output and input.

Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

Command input. When sampled at the rising edge of the clock,

RAS#, CAS# and WE# define the operation to be executed.

Referred to RAS#

Referred to RAS#

The output buffer is placed at Hi-Z(with latency of 2) when DQM

is sampled high in read cycle. In write cycle, sampling DQM

high will block the write operation with zero latency.

System clock used to sample inputs on the rising edge of clock.

CKE controls the clock activation and deactivation. When CKE

is low, Power Down mode, Suspend mode, or Self Refresh

mode is entered.

Power for input buffers and logic circuit inside DRAM.

Ground for input buffers and logic circuit inside DRAM.

Separated power from VCC, used for output buffers to improve

noise.

Separated ground from VSS, used for output buffers to improve

noise.

No connection

Revision 1.0

Publication Release Date: March, 1999

-3-

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