VSC852TV 查看數據表（PDF） - Vitesse Semiconductor
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VSC852TV Datasheet PDF : 16 Pages
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Data Sheet
VSC852
VITESSE
SEMICONDUCTOR CORPORATION
1.6Gb/s 64x64
Crosspoint Switch
switch slice should connect to. The format of the program data is simple binary, where the binary value maps
directly to the switch slice position and/or input port number. For example, program data 0000100/010110
would direct output channel Y4 to connect to input channel A22.
To program the switch core, the address and data (13 bits total) for the given output port must be serially
clocked into the SDIN input. The LOAD pin must be asserted with the last serial program bit to load the pro-
gram data into the on-chip program register. The program data will be held in the register until it is either repro-
grammed or the chip is powered off. The last step to programming the switch core is to transfer the program
data to the registers that control the state of each switch slice. The transfer is completed by asserting the CON-
FIG pin. The CONFIG pin can be used as a strobe to allow multiple program commands to be implemented
simultaneously. The CONFIG pin can also be tied HIGH (always asserted) so the core will reprogram after
every LOAD pulse. See Figure 1.
To read the current programming of the switch core, the desired address to query must be clocked into the
chip’s SDIN port. The format of the program data is the same as for writing. Because of the depth of the on-chip
registers, the address bits must be followed by another 6 CLK cycles so the address data is correctly positioned
in the internal register. The dummy bits that are clocked in during the last 6 bits of the program data will be
overwritten when READ is asserted. As the last dummy bit is clocked in, the READ pin must be asserted to
load the on-chip program data into the shift register used for the serial interface logic. See Figure 2.
Write Cycle Timing
Figure 1: Write Sequence Timing
CLK
SDIN
address
data
A6 A5 A4 A3 A2 A1 A0
D
5
D
4
D
3
D
2
D
1
D
0
SDOUT
A6 A5 A4 A3 A2 A1 A0 D5 D4 D3
LOAD
CONFIG
Read Cycle Timing
Figure 2: Read Sequence Timing
CLK
DIN
address
don't care
A6 A5 A4 A3 A2 A1 A0 X X X X X X
READ
SDOUT
address
data
A6 A5 A4 A3 A2 A1 A0
D
5
D
4
D
3
D
2
D
1
D
0
G52245-0, Rev 4.2
06/01/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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