UT52L1616 查看數據表（PDF） - Utron Technology Inc

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UT52L1616

1M X 16 BIT SDRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.91

UT52L1616

1M X 16 BIT SDRAM

Mode Register Set (MRS)

This command is used to program the SDRAM for the desired operating mode. This command is normally used

after power up as defined in the power up sequence before the actual operation of the SDRAM is initiated. The

functionality of the SDRAM device can be altered by re-programming the mode register through the execution of

Mode Register Set command. Both banks must be precharged (i.e. in idle state) before the MRS command can

be issued.

Mode Register Definition

The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode

register consists of five sections, each of which is assigned to address pins.

A11, A10, A9, A8 : (OP Mode):

The synchronous DRAM has two types of write modes. One is the burst write mode, and the other is the single

write mode. These bits specify write mode.

Burst read and burst write:

Burst write is performed for the specified burst length starting from the column address specified in the write cycle.

Burst read and single write:

Data is only written to the column address specified during the write cycle, regardless of the burst length.

A6, A5, A4: (CAS Latency):

These pins specify the CAS latency.

A3: (BT):

A burst type is specified. When full-page burst is performed, only "sequential" can be selected.

A2, A1, A0: (Burst Length):

These pins specify the burst length.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

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P90004

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