UT52L1616 查看數據表（PDF） - Utron Technology Inc
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UT52L1616 Datasheet PDF : 36 Pages
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UTRON
Preliminary Rev. 0.91
UT52L1616
1M X 16 BIT SDRAM
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
0
LMODE
BT
BL
A6 A5 A4 CAS Latency
0 00
R
0 01
1
0 10
2
0 11
3
1 --
R
A11 A10 A9
000
XX0
001
XX1
A8
Write mode
0 Burst read and burst write
1R
0 Burst read and Single wirte
1R
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0 BT=0 BT=1
000 1
1
001 2
2
010 4
4
011 8
8
100 R
R
101 R
R
110 R
R
1 1 1 F.P. R
F.P.= Full Page(256)
R is Reserved (inhibit)
.= 0 or 1
Burst length = 2
Burst length = 4
Starting Ad.
A0
0
1
Addressing (decimal)
Sequence Interleave
0, 1, 0, 1,
1, 0, 1, 0,
Burst length = 8
Starting Ad.
A1 A0
0
0
0
1
1
0
1
1
Addressing (decimal)
Sequence
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
Interleave
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Starting Ad.
Addressing (decimal)
A2 A1 A0
Sequence
0 0 0 0, 1, 2, 3, 4, 5, 6, 7,
0 0 1 1, 2, 3, 4, 5, 6, 7, 0,
0 1 0 2, 3, 4, 5, 6, 7, 0, 1,
0 1 1 3, 4, 5, 6, 7, 0, 1, 2,
1 0 0 4, 5, 6, 7, 0, 1, 2, 3,
1 0 1 5, 6, 7, 0, 1, 2, 3, 4,
1 1 0 6, 7, 0, 1, 2, 3, 4, 5,
1 1 1 7, 0, 1, 2, 3, 4, 5, 6,
Interleave
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7, 6,
2, 3, 0, 1, 6, 7, 4, 5,
3, 2, 1, 0, 7, 6, 5, 4,
4, 5, 6, 7, 0, 1, 2, 3,
5, 4, 7, 6, 1, 0, 3, 2,
6, 7, 4, 5, 2, 3, 0, 1,
7, 6, 5, 4, 3, 2, 1, 0,
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
14
P90004
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