UT52L1616 查看數據表（PDF） - Utron Technology Inc

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UT52L1616

1M X 16 BIT SDRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.91

UT52L1616

1M X 16 BIT SDRAM

PIN FUNCTIONS

CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising

edge.

CE (input pin): When CE is Low, the command input cycle becomes valid. When CE is High, all inputs are

ignored. However, internal operations (bank active, burst operations, etc.) are held.

RAS , CAS , and WE (input pins): Although these pin names are the same as those of conventional

DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on

the combination of their voltage levels. For details, refer to the command operation section.

A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active

command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read or

write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines

the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when

A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged.

A11 (input pin): A11 is a bank select signal (BS). The memory array of the UT52L1616 is divided into bank 0

and bank 1, both which contain 512 K x 16 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is

selected.

CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising

edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power down and clock

suspend modes.

DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output buffers.

Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is Low, the

output buffer becomes Low-Z.

Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written).If

DQMU/DQML is Low, the data is written.

DQ0 to DQ15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of a

conventional DRAM.

Vcc and VccQ (power supply pins): 3.3V is applied. (Vcc is for the internal circuit and VccQ is for the

output buffer.)

Vss and VssQ (power supply pins): Ground is connected. (Vss is for the internal circuit and VssQ is for the

output buffer.)

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

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P90004

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