MCM72F6A 查看數據表（PDF） - Motorola => Freescale
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MCM72F6A Datasheet PDF : 10 Pages
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MCM72F7A CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70 °C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
W, K
Cin
—
E, G
—
Other Inputs
—
22
pF
36
60
I/O Capacitance
CI/O
—
28
pF
MASS (Periodically Sampled Rather Than 100% Tested)
Parameter
MCM72F6A
MCM72F7A
Max
Unit
16
g
20
g
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20 to 80%)
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . See Figure 1 Unless Otherwise Noted
DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM72F6A–9
MCM72F7A–9
MCM72F6A–10
MCM72F7A–10
MCM72F6A–12
MCM72F7A–12
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
Cycle Time
tKHKH
12
—
15
—
16.6
—
ns
Clock High Pulse Width
tKHKL
4
—
5
—
6
—
ns
Clock Low Pulse Width
tKLKH
4
—
5
—
6
—
ns
Clock Access Time
tKHQV
—
9
—
10
—
12
ns
Output Enable to Output Valid
tGLQV
—
5
—
5
—
6
ns
Clock High to Output Active
tKHQX1
0
—
0
—
0
—
ns
5
Clock High to Output Change
tKHQX2
3
—
3
—
3
—
ns
5
Output Enable to Output Active
tGLQX
0
—
0
—
0
—
ns
5
Output Disable to Q–High–Z
tGHQZ
—
5
—
5
—
6
ns
5, 6
Clock High to Q–High–Z
tKHQZ
3
5
3
5
3
6
ns
5, 6
Setup Times
Address tAVKH
2.5
—
2.5
—
2.5
—
ns
ADSP tADKH
Data In tDVKH
Write tWVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
—
ns
ADSP, ADSC, ADV tKHADX
Data In tKHDX
Write tKHWX
Chip Enable tKHEX
NOTES:
1. In setup and hold times, write refers to any Wx low.
2. Chip Enable is defined as Ex low, whenever ADSP is asserted.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
5. This parameter is sampled and not 100% tested.
6. Measured at ± 200 mV from steady state.
MOTOROLA FAST SRAM
MCM72F6A•MCM72F7A
7
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