MC12429FN 查看數據表（PDF） - Motorola => Freescale

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MC12429FN

High Frequency Clock Generator

Motorola => Freescale 

MC12429

SCLOCK

FREF

MCNT

PLL 12429

M COUNTER

VCO_CLK

0

1

SEL_CLK

SDATA SHIFT

REG

14–BIT T0

T1

T2

LATCH

SLOAD

Reset

PLOADB

DECODE

N DIVIDE

(2, 4, 8, 16)

FOUT

(VIA ENABLE GATE)

FDIV4

MCNT

LOW

FOUT

MCNT

FREF

HIGH

7

TEST

MUX

0

TEST

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin

PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.

Figure 4. Serial Test Clock Block Diagram

DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)

Symbol

Characteristic

Min

Typ

VIH

VIL

IIN

VOH

VOL

VOH

Input HIGH Voltage

Input LOW Voltage

Input Current

Output HIGH Voltage

Output LOW Voltage

Output HIGH Voltage

2.0

TEST

2.5

TEST

FOUT

FOUT

2.17

VOL

Output LOW Voltage

FOUT

FOUT

1.41

ICC

Power Supply Current

VCC

85

PLL_VCC

15

1. Output levels will vary 1:1 with VCC0 variation.

2. 50Ω to VCC – 2.0V pulldown.

Max

Unit

Condition

V

VCC = 3.3 to 5.0V

0.8

V

VCC = 3.3 to 5.0V

1.0

mA

V

IOH = –0.8mA

0.4

V

IOL = 0.8mA

2.50

V

VCC0 = 3.3V (Notes 1., 2.)

1.76

V

VCC0 = 3.3V (Notes 1., 2.)

100

mA

20

TIMING SOLUTIONS

5

BR1333 — Rev 6

MOTOROLA

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