AM93LC66 查看數據表（PDF） - Anachip Corporation

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AM93LC66

4096-bits Serial Electrically Erasable PROM

Anachip Corporation 

4096-bits Serial Electrically Erasable PROM

Pin Capacitance ** (Ta=25°C , f=1MHz )

Symbol

Parameter

COUT

Output capacitance

CIN

Input capacitance

Note ** :The parameter is characterized and isn’t 100% tested.

Max

5

5

ATC

AM93LC66

Units

pF

pF

Functional Descriptions

Applications

The AM93LC66 is ideal for high volume applications

requiring low power and low density storage. This

device uses a low cost, space saving 8-pin package.

Typical applications include robotics, alarm devices,

electronic locks, meters and instrumentation settings

such as LAN cards, monitors and MODEM.

Endurance and Data Retention

The AM93LC66 is designed for applications

requiring up to 1M programming cycles (WRITE,

WRALL, EARSE and ERALL). It provides 40 years

of secure data retention.

Device Operation

The AM93LC66 is controlled by seven 11-bit

instructions. Instructions are clocked in (serially) on

the DI pin. Each instruction begins with a logical "1"

(the start bit). This is followed by the opcode (2 bits),

the address field (8 bits), and data, if appropriate.

The clock signal (SK) may be halted at any time and

the AM93LC66 will remain in its last state. This

allows full static flexibility and maximum power

conservation.

Read (READ)

The READ instruction is the only instruction that

outputs serial data on the DO pin. After the read

instruction and address have been decoded, data is

transferred from the selected memory register into a

8-bit or 16-bit serial shift register. (Please note that

one logical "0" bit precedes the actual 8-bit or 16-bit

output data string.) The output on DO changes

during the rising edge transitions of SK. (Shown in

Figure 3)

Auto Increment Read Operations

Sequential read is possible, since the AM93LC66

has been designed to output a continuous stream of

memory content in response to a single read

operation instruction. To utilize this function, the

system asserts a read instruction specifying a start

location address. Once the 8-bit or 16-bit of the

addressed word have been clocked out, the data in

consecutively higher address locations is output.

The address will wrap around continuously with CS

high until the chip select (CS) control pin is brought

low. This allows for single instruction data dumps to

be executed with a minimum of firmware overhead.

Write Enable (WEN)

Before any device programming (WRITE, WRALL,

ERASE, and ERAL) can be done, the WRITE

ENABLE (WEN) instruction must be executed first.

When Vcc is applied, this device powers up in the

WRITE DISABLE state. The device then remains in

a WRITE DISABLE state until a WEN instruction is

executed. Thereafter the device remains enabled

until a WDS instruction is executed or until Vcc is

removed. (NOTE: Neither the WEN nor the WDS

instruction has any effect on the READ instruction.)

(Shown in Figure 4)

Write Disable (WDS)

The WRITE DISABLE (WDS) instruction disables all

programming capabilities. This protects the entire

part against accidental modification of data until a

WEN instruction is executed. (When Vcc is applied,

this part powers up in the WRITE DISABLE state.)

To protect data, a WDS instruction should be

executed upon completion of each programming

operation. (NOTE: Neither the WEN nor the WDS

instruction has any effect on the READ instruction.)

(Shown in Figure 5)

Anachip Corp.

www.anachip.com.tw

Rev. A1 Oct 20, 2003

4/10

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