NCP1232DR2 查看數據表（PDF） - ON Semiconductor

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NCP1232DR2

Microprocessor Monitor

ON Semiconductor 

NCP1232

tPB

PB RST

tPBD

VIL

RST

RST

VIH

tRST

Figure 3. Push-button Reset. The debounced PB RST

input ignores input pulses less than 1 msec and is

guaranteed to recognized pulses of 20 msec or greater

PUSH-BUTT ON RESET

tST

ST

tTD

Figure 4. Strobe Input

NOTE: tTD is the maximum elapsed time between ST high-to-low

transistions (ST is activated by falling edges only) which will

keep the watchdog timer from forcing the reset outputs active

for a time of tRST. tTD is a function of the voltage at the TD pin,

as tabulated below.

CONDITION

tTD

MIN

TYP

MAX

TD PIN = 0 V 62.5 msec

TD PIN = OPEN

TD PIN = VCC 500 msec

150 msec

250 msec

1200 msec

250 msec

600 msec

2000 msec

1000 msec

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