AS7C33256PFD18A(2002) 查看數據表（PDF） - Alliance Semiconductor
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AS7C33256PFD18A Datasheet PDF : 11 Pages
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AS7C33256PFD16A
AS7C33256PFD18A
®
Functional description
The 7C33256PFD16A and AS7C33256PFD18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 5.0/5.4/6.0/7.5/10 ns with clock access times (tCD) of 3.0/3.1/3.5/4.0/5.0 ns enable 200, 183, 166, 133 and 100 MHz
bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst
addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium® count
sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33256PFD16A and 7C33256PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V.
These devices are available in a 100-pin 14×20 mm TQFP packaging.
Capacitance
Parameter
Symbol
Signals
Test conditions
Max Unit
Input capacitance
CIN
I/O capacitance
CI/O
Write enable truth table (per byte)
Address and control pins
I/O pins
VIN = 0V
VIN = VOUT = 0V
5
pF
7
pF
GWE
BWE
BWn
WEn
L
X
X
T
H
L
L
T
H
H
X
F*
H
L
H
F*
Key: X = Don’t Care, L = Low, H = High, T=True, F=False; *=valid read; n = a,b; WE, WEn = internal write signal
Burst Order
Interleaved Burst Order
LBO=1
Starting Address 00 01 10 11
First increment 01 00 11 10
Second increment 10 11 00 01
Third increment 11 10 01 00
Starting Address
First increment
Second increment
Third increment
Linear Burst
OrderLBO=0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
1. PowerPC™ is a trademark International Business Machines Corporation.
3/8/02; v.1.6
Alliance Semiconductor
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