DS1667-50 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1667-50

Digital Resistor with OP AMP

Dallas Semiconductor -> Maxim Integrated 

DS1667

Valid data is entered into the I/O shift register while RST is high on the low-to-high transition of the

CLK input. Data input on the DQ pin can be changed while the clock input is high or low, but only data

meeting the setup requirements will enter the shift register. Data is always entered starting with the value

of the stack select bit. The next 8 bits to be entered are those specifying the wiper 1 setting. The MSB of

these 8 bits is sent first. The next 8 bits to be entered are those specifying the wiper 0 setting, sent MSB

first. The 17th bit to be entered, therefore, will be the least significant bit of the wiper 0 setting. If fewer

than 17 bits are entered, the value of the potentiometer settings will result from the number of bits that

were entered plus the remaining bits of the old value shifted over by the number of bits sent. If more than

17 bits are sent, only the last 17 bits are left in the shift register. Therefore, sending other than 17 bits can

produce indeterminate potentiometer settings.

As bits are entered into the shift register, the previous value is shifted out bit by bit on the cascade serial

port pin (COUT). By connecting the COUT pin to the DQ pin of a second DS1667, multiple devices can

be daisy chained together as shown in Figure 3.

When connecting multiple devices, the total number of bits sent is always 17 times the number of

DS1667s in the daisy chain. In applications where it is desirable to read the settings of potentiometers, the

COUT pin of the last device connected in a daisy chain must be connected back to the DQ input of the

first device through a resistor with a value of 1k to 10k. This resistor provides isolation between COUT

and DQ when writing to the device (see Figure 3).

When reading data, the DQ line is left floating by the reading device. When RST is held low, bit 17 is

always present on the COUT pin, which is fed back to the input DQ pin through the resistor (see Figure

4). This data bit can now be read by the reading device. The RST pin is then transitioned high to initiate a

data transfer. When the CLK input transitions low to high, bit 17 is loaded into the first position of the

I/O shift register and bit 16 becomes present on COUT and DQ. After 17 bits (or 17 times the number of

devices for a daisy chain), the data has shifted completely around and back to its original position. When

RST is transitioned back low to end data transfer, the value (the same as before the read occurred) is

loaded into the wiper 0 and wiper 1 registers and the stack select bit.

When power is applied to the DS1667, the device always has the wiper settings at half position and the

stack select bit is at 0.

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