ICS9150-01 查看數據表（PDF） - Integrated Circuit Systems
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ICS9150-01 Datasheet PDF : 14 Pages
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ICS9150- 01
Power-On Conditions
SEL 66/60#
1
0
1
0
MODE
1
1
0
0
PIN #
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 33, 32, 25,
24
9, 11, 12, 13, 14,
16, 8
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 33, 32, 25,
24
9, 11, 12, 13, 14,
16, 8
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 25, 24
33
32
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 25, 24
33
32
DES C RIP TIO N
CPUCLKs
F UN C TIO N
66.6 MHz - w/serial config enable/disable
SDRAM
66.6 MHz - All SDRAM outputs
PCICLKs
CPUCLKs
SDRAM
33.3 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
PCICLKs
CPUCLKs
SDRAM
PCI_STOP#
CPU_STOP#
CPUCLKs
SDRAM
PCI_STOP#
CPU_STOP#
30 MHz - w/serial config enable/disable
66.6 MHz - w/serial config enable/disable
66.6 MHz - All SDRAM outputs
Power Management, PCI (0:5) clocks stopped when low
Power Managemen, CPU clocks stopped when low
60 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
Power Management, PCI (0:5) clocks stopped when low
Power Managemen, CPU clocks stopped when low
Example:
a) if MODE = 1, pins 33 and 32 are configured as SDRAM12, and SDRAM13 respectively.
b) if MODE = 0, pins 33 and 32 are configured as PCI_STOP#, and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.
C LO C K
REF 0
IOAPIC (0:2)
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
3
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