ICS9150-01 查看數據表（PDF） - Integrated Circuit Systems

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ICS9150-01

Pentium Pro™ and SDRAM Frequency Generator

Integrated Circuit Systems 

ICS9150- 01

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9150-01. It is used to turn off the PCICLK (0:5) clocks for low power

operation. PCI_STOP# is synchronized by the ICS9150-01 internally. The minimum that the PCICLK (0:5) clocks are enabled

(PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with

a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one

PCICLK clock.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9150 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the ICS9150.

3. All other clocks continue to run undisturbed.

4. CPU_STOP# is shown in a high (true) state.

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