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IDT54FCT162H272ATE 查看數據表(PDF) - Integrated Device Technology

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IDT54FCT162H272ATE
IDT
Integrated Device Technology IDT
IDT54FCT162H272ATE Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162H272AT
FCT162H272CT
FCT162H272ET
Symbol
Parameter
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay
CL = 50pF 1.5 5.8 1.5 6.2 1.5 5.2 1.5 5.6 1.5 4.8 — — ns
tPHL CLK to 1Bx or CLK to 2Bx
RL = 500
tPLH Propagation SEL Stable
tPHL Delay
CExB Enabled
1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.0 — — ns
CLK to Ax SEL Changing
CExB Disabled
1.5 6.0 1.5 6.4 1.5 5.4 1.5 5.8 1.5 5.4 — — ns
SEL Changing
CExB Enabled
1.5 7.6 1.5 7.9 1.5 6.6 1.5 7.0 1.5 5.6 — — ns
tPZH Output Enable Time
1.5 7.7 1.5 8.1 1.5 6.8 1.5 7.2 1.5 6.0 — — ns
tPZL CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
tPHZ Output Disable Time
1.5 6.4 1.5 6.8 1.5 6.0 1.5 6.4 1.5 5.6 — — ns
tPLZ CLK to Ax, CLK to 1Bx, or
CLK to 2Bx
tSU Set-Up Time, HIGH or LOW
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns
Data to CLK
tSU Set-Up Time, OEA to CLK,
OEB to CLK
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns
tSU Set-Up Time, SEL to CLK
tSU Set-Up Time, CEA1B to CLK,
CE1B to CLK, CE2B to CLK,
or CEA2B to CLK
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns
2.0 — 2.0 — 2.0 — 2.0 — 2.0 — — — ns
tH Hold Time, CLK to Data
tH Hold Time, CLK to OEA,
CLK to OEB, CLK to SEL
tH Hold Time, CLK to CEA1B,
CLK to CE1B, CLK to CE2B,
CLK to CEA2B
tW Pulse Width, CLK HIGH(4)
tSK(o) Output Skew(3)
0 — 0 — 0 — 0 — 0 — — — ns
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — — ns
0 — 0 — 0 — 0 — 0 — — — ns
3.0 — 3.0 — 3.0 — 3.0 — 3.0 — — — ns
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
3071 tbl 10
5.5
6

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