IDT70V657S 查看數據表（PDF） - Unspecified

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IDT70V657S

HIGH-SPEED 3.3V 32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

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IDT70V657S

High-Speed 3.3V 32K x 36 Asynchronous Dual-Port Static RAM

Preliminary

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

CE0L, CE1L

R/WL

CE0R, CE1R

R/WR

Chip Enables

Read/Write Enable

OEL

OER

Output Enable

A0L - A14L

A0R - A14R

Address

I/O0L - I/O35L

I/O0R - I/O35R

Data Input/Output

SEML

SEMR

Semaphore Enable

INTL

INTR

Interrupt Flag

BUSYL

BUSYR

Busy Flag

BE0L - BE3L

VDDQL

BE0R - BE3R

VDDQR

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)(1)

OPTL

OPTR

Option for selecting VDDQX(1,2)

M/S

Master or Slave Select

VDD

Power (3.3V)(1)

VSS

TDI

TDO

TCK

TMS

TRST

Ground (0V)

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

5615 tbl 01

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

5

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