MAX791M(1995) 查看數據表（PDF） - Maxim Integrated
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MAX791M Datasheet PDF : 20 Pages
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Microprocessor Supervisory Circuit
4.65V
VCC 3
1
VBATT
150mV
CHIP-ENABLE
OUTPUT
CONTROL
10
LOWLINE
5
BATT ON
2 VOUT
13
CE IN VOUT
9
MR
8
SWT
11
WDI
7
PFI
1.25V
12 CE OUT
RESET
GENERATION
TIMEBASE FOR
RESET AND
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
15 RESET
16 WDPO
14 WDO
6 PFO
4 GND
MAX791
Figure 1. Block Diagram
MR
RESET
CE IN
0V
CE OUT
25µs MIN
7.5µs TYP
15µs TYP
Figure 2. Manual-Reset Timing Diagram
MANUAL RESET
*
OTHER
RESET
SOURCES
*
MR
MAX791
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
tFoigcuornen3e.ctDtoioM–d—eR–."OR" connections allow multiple reset sources
_______________Detailed Description
Manual Reset Input
Many µP-based products require manual-reset capabil-
ity, allowing the operator or test technician to initiate a
reset. The Manual Reset Input (MR) can be connected
directly to a switch, without an external pull-up resistor
or debouncing network. It connects to a 1.25V com-
parator, and has a pull-up to VOUT as shown in Figure
1. The propagation delay from asserting MR to RESET
asserted is 4µs typical. Pulsing MR low for a minimum
of 15µs resets all the internal counters, sets the
Watchdog Output (WDO) and Watchdog-Pulse Output
(WDPO) high, and sets the Set Watchdog-Timeout
(SWT) input to VOUT - 0.6V, if it is not already connect-
ed to VOUT (for internal timeouts). It also disables the
chip-enable function, setting the Chip-Enable Output
(CE OUT) to a high state. The RESET output remains
active as long as MR is held low, and the reset-timeout
period begins after MR returns high (Figure 2).
Use this input as either a digital-logic input or a second
low-line comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
8 _______________________________________________________________________________________
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