QL7120-5PT208M 查看數據表（PDF） - QuickLogic Corporation

零件编号

产品描述 (功能)

生产厂家

QL7120-5PT208M

Combining Performance, Density and Embedded RAM

QuickLogic Corporation 

4/ (FOLSVH3OXV 'DWD 6KHHW 5HY $

Quad net

)LJXUH  (FOLSVH3OXV *OREDO &ORFN 6WUXFWXUH

&ORFN 6RXUFH

Logic Cells (Internal)

Clock Pad

7DEOH  (FOLSVH3/XV &ORFN 'HOD\

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

*OREDO

'HGLFDWHG

Clock signal generated internally 1.51 ns (max)

Clock signal generated externally 2.06 ns (max)

1.73 ns (max)

&ORFN 6HJPHQW

tPGCKa

tBGCK

7DEOH  (FOLSVH3OXV *OREDO &ORFN 'HOD\

3DUDPHWHU

0LQ

Global clock pin delay to quad net

-

Global clock tree delay (quad net to

flip-flop)

-

9DOXH

0D[

1.34 ns

0.56 ns

D :KHQ XVLQJ D 3// W3*&. DQG W%*&. DUH HIIHFWLYHO\ ]HUR GXH WR GHOD\ DGMXVWPHQW E\ 3KDVH

/RFNHG /RRS



WWWWWW ZZZTXLFNORJLFFRP

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

tPGCK

Clock

Select

tBGCK

)LJXUH  *OREDO &ORFN 6WUXFWXUH 6FKHPDWLF

‹  4XLFN/RJLF &RUSRUDWLRQ

Share Link: