QL7120-5PT208M 查看數據表（PDF） - QuickLogic Corporation

零件编号

产品描述 (功能)

生产厂家

QL7120-5PT208M

Combining Performance, Density and Embedded RAM

QuickLogic Corporation 

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[9:0]

[17:0]

WA

RE

WD

WE

WCL K

RCLK

[9:0]

RA

[17:0]

RD

ASYNCRD

RAM Module

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tSWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the

active edge of the WRITE CLOCK

0.675 ns

-

tHWA

WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active

edge of the WRITE CLOCK

0 ns

-

tSWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active

edge of the WRITE CLOCK

0.654 ns

-

tHWD

WD hold time to WCLK: time the WRITE DATA must be stable after the active edge

of the WRITE CLOCK

0 ns

-

tSWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active

edge of the WRITE CLOCK

0.623 ns

-

tHWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active

edge of the WRITE CLOCK

0 ns

-

tWCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the

time when the data is available at RD

-

4.38 ns

WCLK

WA

tSWA

tHWA

WD

tSWD

tHWD

WE

tSWE

tHWE

RD

old data

new data

tWCRD

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