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SL1710 查看數據表(PDF) - Zarlink Semiconductor Inc

零件编号
产品描述 (功能)
生产厂家
SL1710
ZARLINK
Zarlink Semiconductor Inc ZARLINK
SL1710 Datasheet PDF : 12 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Preliminary Information SL1710
ELTEaCmTbR=I0CoACLtoC8H0oACR, AVeCeT=E0RVI,SVTccIC=S4.7(5coton5t.i2n5uVe,dT)hese characteristics are guaranteed by either production test or design.
They apply within the specified ambient temperature and supply voltage unless otherwise stated.
Characteristic
Prescaler sidebands
Power supply rejection
Value
Pin
Min
Typ
Max
Units
Conditions
2, 7
-50
-47
dBV Measured in IQ outputs
2, 7
25
30
dB Attenuation VCC to IQ outputs,
over 0-500kHz
Notes:
1. The choice of L will have an effect on phase noise of the VCO
2. Target value at fo=500MHz, L (tank)=10nH, Q (tank, unloaded)=50, SSB
DESCRIPTION
The SL1710 is a quadrature downconverter, intended for
high linearity, low noise digital satellite applications. It contains
all the elements necessary, with the exception of the VCO
tuning components, to extract baseband I and Q signals from
a QPSK or QAM IF input signal.
A block diagram for the SL1710 is shown in Fig. 2.
In normal consumer digital satellite applications, the device
is fed via a SAW filter, centred at the standard IF of 479.5MHz.
A filtered single channel is therefore presented to the device,
at a typical level of -51dBV. An AGC is included with 18dB of
gain control, which is guaranteed to provide an overall conver-
sion gain between 30 and 45dB from the RF input to the I and
Q outputs.
The quadrature mixers are fed from an on-chip oscillator
which is centred on the incoming IF. The oscillator external
tuning network should be fully symmetric, to ensure optimum
gain and phase match.
Single ended I and Q amplifiers are provided, which output
a 760mV (p/p) signal, assuming a nominal -51dBV input signal
and 40dB gain, suitable for driving a dual channel ADC such as
the PCA 869, PCA 913 and PCA 916 via an anti-alias filter (see
application notes). The ADC is normally AC coupled via two
capacitors (typically 4.7µF).
The SL1710 also includes divide by 32 prescaler output.
These may be fed to an external PLL circuit which can be used
to drive the on-chip oscillator, thus forming a complete control
loop.
The VCO can be disabled by applying 0V to pin 15.
3

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