SPC5605BF1ACMG4 查看數據表（PDF） - NXP Semiconductors.
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SPC5605BF1ACMG4 Datasheet PDF : 112 Pages
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Package pinouts and signal descriptions
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A PC[8]
PC[13] PH[15] PJ[4]
PH[8] PH[4]
PC[5]
PC[0]
PI[0]
PI[1]
PC[2]
PI[4] PE[15] PH[11]
NC
NC A
B PC[9]
PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2]
PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B
C PC[14] VDD_HV PB[3]
PE[7]
PH[7]
PE[5]
PE[3] VSS_LV PC[1]
PI[3]
PA[5]
PI[5] PE[14] PE[12] PA[9]
PA[8] C
D PH[14]
PI[6] PC[15] PI[7]
PH[6]
PE[4]
PE[2] VDD_LV VDD_HV NC
PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D
E PG[4]
PG[5] PG[3] PG[2]
PG[1] PG[0] PF[15] VDD_HV E
F PE[0]
PA[2]
PA[1] PE[1]
PH[0] PH[1] PH[3] PH[2] F
G PE[9]
PE[8] PE[10] PA[0]
VSS_HV VSS_HV VSS_HV VSS_HV
VDD_HV PI[12] PI[13] MSEO G
H VSS_HV PE[11] VDD_HV NC
VSS_HV VSS_HV VSS_HV VSS_HV
MDO3 MDO2 MDO0 MDO1 H
J RESET VSS_LV NC
NC
K EVTI
NC VDD_BV VDD_LV
L
PG[9]
PG[8]
NC
EVTO
VSS_HV VSS_HV VSS_HV VSS_HV
VSS_HV VSS_HV VSS_HV VSS_HV
PI[8]
PI[9]
PI[10] PI[11] J
VDD_HV
_ADC1
PG[12]
PA[3]
PG[13] K
PB[15] PD[15] PD[14] PB[14] L
M PG[7]
PG[6] PC[10] PC[11]
PB[13] PD[13] PD[12] PB[12] M
N PB[1]
P PF[8]
R PF[12]
T
NC
PF[9]
PB[0] VDD_HV PJ[0]
PA[4] VSS_LV EXTAL VDD_HV PF[0]
PJ[3]
PC[7]
PJ[2]
PJ[1] PA[14] VDD_LV XTAL PB[10] PF[1]
PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] PI[14] XTAL32 PF[3]
NC
NC
MCKO
NC
PF[13] PA[12]
PI[15]
EXTAL
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PF[2]
PF[4]
VSS_HV
_ADC1
PB[11]
PD[10]
PD[9]
PD[11] N
PF[5]
PD[0]
PD[3]
VDD_HV
_ADC0
PB[6]
PB[7] P
PF[7]
PD[2]
PD[4]
PD[7]
VSS_HV
_ADC0
PB[5]
R
PF[6]
PD[1]
PD[5]
PD[6]
PD[8]
PB[4] T
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NOTE: The 208 MAPBGA is available only as development package for Nexus 2+.
NC = Not connected
Figure 5. 208 MAPBGA configuration
3.2 Pad configuration during reset phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are tristate with the following exceptions:
• PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from flash.
• PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset.
• RESET pad is driven low by the device till 40 FIRC clock cycles after phase2 completion. Minimum phase3 duration
is 40 FIRC cycles.
• Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.
MPC5607B Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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