STK672 查看數據表（PDF） - SANYO -> Panasonic
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STK672 Datasheet PDF : 11 Pages
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STK672-050
Design material
1. Explanation of input pins
Pin No.
14
15
17
18
9, 10, 11
12, 13
16
8
Name
CLK
CWB
RETURN
ENABLE
M1, M2, M3
M4, M5
RESET
Vref
Function
Phase switching clock
Setting of rotation direction (CW/CCW)
Phase origin forced return
Output cut-off
Setting of excitation mode
Setting of vector locus
System reset
Setting of current value
Pin format
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
CMOS Schmitt configuration with pull-up resistor
2. Functions and timing of input signals
2-1. CLK (Phase switching clock)
1. Input frequency range sDC to 50 kHz
2. Minimum pulse width s10 µs
3. Duty
s40 to 60%
4. Pin format
sCMOS Schmitt configuration containing pull-up resistor (20 kΩ typical value)
5. Noise eliminating circuit with multiple stages is contained.
6. Functions
a. When the signal M3 is set to 1 or it is opened.
The excitation phase moves at each step at the rising edge of the clock.
b. When the signal M3 is set to 0.
The excitation phase moves at each step at the rising and falling edges of the clock.
2-2. CWB (Setting of rotation direction)
1. Pin format
sCMOS Schmitt configuration containing pull-up resistor
(20kΩ, typical value)
2. Function
a. When the signal CWB is set to 1.
It rotates clockwise.
b. When the signal CWB is set to 0.
It rotates counterclockwise.
3. Note
sWhen the signal M3 is set to 0, the CWB input signal must not be changed
at the rising edge and falling edge of the clock input for the period of 5 µs.
No. 5228—5/11
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