STM817L 查看數據表（PDF） - STMicroelectronics
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STM817L Datasheet PDF : 43 Pages
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Description
STM690A/692A/703/704/802/805/817/818/819
Figure 5. STM703/704/819 connections
VOUT
VCC
VSS
PFI
SO8/TSSOP8
1
8
2
7
3
6
4
5
VBAT
RST
MR
PFO
AI07890
Figure 6. STM818 connections
VOUT
VCC
VSS
E
SO8/TSSOP8
1
8
2
7
3
6
4
5
VBAT
RST
WDI
ECON
AI07892
1.1
1.1.1
1.1.2
1.1.3
1.1.4
Pin descriptions
MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active-low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
WDI
If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is
triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a
rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
RST
Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold
or when MR is a logic low. It remains low for trec after either VCC rises above the reset
threshold, the watchdog triggers a reset, or MR goes from low to high.
RST
Pulses high for trec when triggered, and stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
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Doc ID 10522 Rev 10
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