STV0118 查看數據表（PDF） - STMicroelectronics

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STV0118

PAL/NTSC HIGH PERFORMANCE DIGITAL ENCODER

STMicroelectronics 

STV0118

IV - FUNCTIONAL DESCRIPTION (continued)

Figure 8 : Horizontal Blanking Interval and Active Video Timings

d

0H

b

a

c1 (bit ”aline” = 0)

c2 (bit ”aline” = 1)

Full Digital Line Encoding

(720 Pixels - 1440T)

”Analog” Line Encoding

(710 Pixels - 1420T)

NTSC-M

a

5.38µs (even lines)

5.52µs (odd lines)

PAL-BDGHI

5.54µs (A-type)

5.66µs (B-type)

PAL-N

5.54µs (A-type)

5.66µs (B-type)

PAL-M

5.73µs (A-type)

5.87µs (B-type)

These are typical values.

Actual values will depend on the static offset programmed for subcarrier generation.

b

1.56µs

1.28µs

1.28µs

1.28µs

c1

8.8µs

c2

9.3µs

9.3µs

10.1µs

9.3µs

10.1µs

9.3µs

10.1µs

d 9 Cycles of 3.58MHz 10 Cycles of 4.43MHz 9 Cycles of 3.58MHz 9 Cycles of 3.58MHz

IV.3 - Reset Procedure

Ahardware reset is performedby grounding the pin

NRESET. The master clock must be running and

pin NRESET kept low for a minimum of 5 clock

cycles. This sets the STV0118 in HSYNC+ODDEV

(line-locked) slave mode, for NTSC-M, interlaced

ITU-R601 encoding. Closed-captioning and

Teletext encoding are all disabled.

Then the configuration can be customized by wri-

ting into the appropriate registers. A few registers

are never reset, their contents is unknown until the

first loading (refer to the Register Contents and

Description).

It is also possible to perform a software reset by

setting bit’softreset’ in Reg 6. The IC’s response in

that case is similar to its response after a hardware

reset, except that Configuration Registers

(Reg 0 to 6) and a few other registers (see descrip-

tion of bit ‘softreset’) are not altered .

10/42

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