ST72F325AR(2007) 查看數據表（PDF） - STMicroelectronics

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ST72F325AR
(Rev.:2007)

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface

STMicroelectronics 

1 DESCRIPTION

The ST72F325 Flash and ST72325 ROM devices

are members of the ST7 microcontroller family de-

signed for mid-range applications.

They are derivatives of the ST72321 and ST72324

devices, with enhanced characteristics and robust

Clock Security System.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with Flash or ROM pro-

gram memory. The ST7 family architecture offers

both power and flexibility to software developers,

enabling the design of highly efficient and compact

application code.

The on-chip peripherals include an A/D converter,

a PWM Autoreload timer, 2 general purpose tim-

ers, I2C bus, SPI interface and an SCI interface.

For power economy, microcontroller can switch

dynamically into WAIT, SLOW, ACTIVE-HALT or

Figure 1. Device Block Diagram

HALT mode when the application is in idle or

stand-by state.

Typical applications are consumer, home, office

and industrial products.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Main Differences with ST72321:

– LQFP48 and LQFP32 packages

– Clock Security System

– Internal RC, Readout protection, LVD and PLL

without limitations

– Negative current injection not allowed on I/O port

PB0 (instead of PC6).

– External interrupts have Exit from Active Halt

mode capability.

RESET

VPP

TLI

VSS

VDD

EVD

OSC1

OSC2

8-BIT CORE

ALU

CONTROL

LVD

AVD

OSC

MCC/RTC/BEEP

PROGRAM

MEMORY

(16K - 60K Bytes1))

RAM

(512 - 2048 Bytes1))

WATCHDOG

DEBUG MODULE

I2C

PF7:0

(8 bits on AR devices)

(6 bits on C/J devices)

(5 bits on K devices)

PORT F

TIMER A

BEEP

PORT A

PORT B

PWM ART

PE7:0

(8 bits on AR devices)

(2 bits on C/J/K devices)

PORT E

SCI

PORT C

TIMER B

PORT D

PD7:0

SPI

(8 bits on AR devices)

(6 bits on C/J devices)

10-BIT ADC

(2 bits on K devices)

VAREF

VSSA

1) ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.

PA7:0

(8 bits on AR devices)

(5 bits on C/J devices)

(4 bits on K devices)

PB7:0

(8 bits on AR devices)

(5 bits on C/J devices)

(3 bits on K devices)

PC7:0

(8 bits)

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