ST72F325K 查看數據表（PDF） - STMicroelectronics

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ST72F325K

8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72325

1 INTRODUCTION

The ST72F325 Flash and ST72325 ROM devices

are members of the ST7 microcontroller family de-

signed for mid-range applications.

They are derivatives of the ST72321 and ST72324

devices, with enhanced characteristics and robust

Clock Security System.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set and are available with FLASH or ROM pro-

gram memory.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or stand-by state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

Figure 1. Device Block Diagram

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

The devices feature an on-chip Debug Module

(DM) to support in-circuit debugging (ICD). For a

description of the DM registers, refer to the ST7

ICC Protocol Reference Manual.

Main Differences with ST72321:

– TQFP48 and TQFP32 packages

– Clock Security System

– Internal RC, Readout protection, LVD and PLL

without limitations

– Negative current injection not allowed on I/O port

PB0 (instead of PC6).

– External interrupts have Exit from Active Halt

mode capability.

RESET

VPP

TLI

VSS

VDD

EVD

OSC1

OSC2

8-BIT CORE

ALU

CONTROL

LVD

AVD

OSC

MCC/RTC/BEEP

PROGRAM

MEMORY

(16K - 60K Bytes1))

RAM

(512 - 2048 Bytes1))

WATCHDOG

DEBUG MODULE

I2C

PF7:0

(8 bits on AR devices)

(6 bits on C/J devices)

(5 bits on K devices)

PORT F

TIMER A

BEEP

PORT A

PORT B

PWM ART

PE7:0

(8 bits on AR devices)

(2 bits on C/J/K devices)

PORT E

SCI

PORT C

TIMER B

PORT D

PD7:0

SPI

(8 bits on AR devices)

(6 bits on C/J devices)

10-BIT ADC

(2 bits on K devices)

VAREF

VSSA

1) ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.

PA7:0

(8 bits on AR devices)

(5 bits on C/J devices)

(4 bits on K devices)

PB7:0

(8 bits on AR devices)

(5 bits on C/J devices)

(3 bits on K devices)

PC7:0

(8 bits)

7/193

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