TSL26725(2016) 查看數據表（PDF） - austriamicrosystems AG
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TSL26725 Datasheet PDF : 46 Pages
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TSL2672 − Absolute Maximum Ratings
Figure 9:
Wait Characteristics; VDD = 3 V, TA = 25°C, WEN = 1 (unless otherwise noted)
Parameter
Test
Conditions
Wait step size
WTIME = 0xFF
Wait number of integration steps (1)
Channel Min Typ Max Unit
2.58 2.73 2.9
ms
1
256 steps
Note(s):
1. Parameter ensured by design and is not tested.
Figure 10:
AC Electrical Characteristics; VDD = 3 V, TA = 25°C, (unless otherwise noted)
Symbol
Parameter (1)
f(SCL)
t(BUF)
t(HDSTA)
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
tR
Ci
Clock frequency (I²C only)
Bus free time between start and stop
condition
Hold time after (repeated) start
condition. After this period, the first
clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Clock/data fall time
Clock/data rise time
Input pin capacitance
Test
Conditions
Min Typ Max Unit
0
400 kHz
1.3
μs
0.6
μs
0.6
μs
0.6
μs
0
μs
100
ns
1.3
μs
0.6
μs
300 ns
300 ns
10
pF
Note(s):
1. Specified by design and characterization; not production tested.
ams Datasheet
[v1-00] 2016-Mar-23
Page 9
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