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WE128K32P-140G2TM 查看數據表(PDF) - White Electronic Designs => Micro Semi

零件编号
产品描述 (功能)
生产厂家
WE128K32P-140G2TM
White-Electronic
White Electronic Designs => Micro Semi White-Electronic
WE128K32P-140G2TM Datasheet PDF : 15 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
FIG. 11
SOFTWARE DATA PROTECTION
DISABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
(3)
EXIT DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
WE128K32-XXX
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the WE-
128K32-XXX has the feature disabled. Write access to the
device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three byte write sequence to permit writing.
After setting software data protection, any attempt to write to
the device without the three-byte command sequence will start
the internal write timers. No data will be written to the device,
however, for the duration of tWC. The write protection feature
can be disabled by a six byte write sequence of specific data to
specific locations. Power transitions will not reset the
software write protection.
Each 128K byte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE128K32-XXX. These are included to improve reliability
during normal operation:
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait 5msec
typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE low and either CS or WE high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a write
cycle.
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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