WED9LAPC2C16V4BC 查看數據表（PDF） - White Electronic Designs => Micro Semi
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WED9LAPC2C16V4BC Datasheet PDF : 23 Pages
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WED9LAPC2C16V4BC
SDRAM CURRENT STATE TRUTH TABLE (cont.)
Current State
Refreshing
Mode Register
Accessing
VCRAS VCCAS
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
Command
VCWE VCBS
VCADDR
Description
Action
Notes
L
OP Code
Mode Register Set
ILLEGAL
H
X
X
Auto or Self Refresh
ILLEGAL
L
X
X
Precharge
ILLEGAL
H
BA Row Address Bank Activate
ILLEGAL
L
BA
Column
Write
ILLEGAL
H
BA
Column
Read
ILLEGAL
L
X
X
Burst Termination
No Operation; Idle after tRC
H
X
X
No Operation
No Operation; Idle after tRC
L
OP Code
Mode Register Set
ILLEGAL
H
X
X
Auto or Self Refresh
ILLEGAL
L
X
X
Precharge
ILLEGAL
H
BA Row Address Bank Activate
ILLEGAL
L
BA
Column
Write
ILLEGAL
H
BA
Column
Read
ILLEGAL
L
X
X
Burst Termination
ILLEGAL
H
X
X
No Operation No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is
illegal. If VCBS selects the bank not being referenced by the Current State then the action may be
legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The VCRAS to VCCAS Delay (tRCD) must occur before the command is given.
5. Address VCADDR9/AP is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank-to-bank delay time (tRRD) is not satisfied.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
10
July 2000 Rev. 0
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