WED9LAPC2C16V4BC 查看數據表（PDF） - White Electronic Designs => Micro Semi
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WED9LAPC2C16V4BC Datasheet PDF : 23 Pages
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WED9LAPC2C16V4BC
SDRAM COMMAND TRUTH TABLE
FUNCTION
Mode Register Set
Auto Refresh (CBR)
Precharge
Single Bank
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Data Write/Output Disable
Data Mask/Output Disable
VCRAS
L
L
L
L
L
H
H
H
H
H
H
X
X
VCCAS
L
L
H
H
H
L
L
L
L
H
H
X
X
VCWE
L
H
L
L
H
L
L
L
H
L
H
X
X
VCDQM
X
X
X
X
X
X
X
X
X
X
X
L
H
VCBS
VCADDR
OP CODE
X
X
BA
L
X
H
BA Row Address
BA
L
BA
H
BA
L
BA
H
X
X
X
X
X
X
X
X
NOTES
2
2
2
2
2
2
3
4
4
NOTES:
1. All of the SDRAM operations are defined by states of VCWE, VCRAS, VCCAS, and VCDQM at the positive rising edge of the clock.
2. Bank Select (VCBS), if VCBS = 0 then bank A is selected, if VCBS = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The VCDQM has two functions for the data DQ Read and Write operations. During a Read cycle, when VCDQM goes high at a clock timing the data outputs are
disabled and become high impedance after a two clock delay. VCDQM also provides a data mask function for Write cycles. When it activates, the Write operation at
the clock is prohibited (zero clock latency).
July 2000 Rev. 0
7
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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