M5M5256DFP 查看數據表（PDF） - Renesas Electronics
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M5M5256DFP Datasheet PDF : 8 Pages
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(3) TIMING DIAGRAMS
Read cycle
A 0~ 14
/S
/OE
DQ1~ 8
/W = "H" lev el
(Note 3)
(Note 3)
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S)
ta (OE)
ten (OE)
ten (S)
tv (A)
tdis (S)
tdis (OE)
DATA VALID
(Note 3)
(Note 3)
Write cycle (/W control mode)
tCW
A 0~ 14
/S
/OE
/W
DQ1~ 8
(Note 3)
tsu (S)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (OE)
(Note 3)
tdis (W)
ten(OE)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
5
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