M5M54R04J-12 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M54R04J-12 Datasheet PDF : 6 Pages
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MITSUBISHI LSIs
M5M54R04J-12,-15
4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle 1
A 0~19 VIH
VIL
DQ1~4 VOH
VOL
tv (A)
PREVIOUS DATA VALID
W=H
S=L
OE=L
t CR
ta(A)
UNKNOWN
tv (A)
DATA VALID
Read cycle 2 (Note 4)
VIH
S
VIL
t CR
ta(S)
(Note 5)
ten (S)
(Note 5)
tdis(S)
DQ1~4 VOH
VOL
ICC1
Icc
ICC2
W=H
OE=L
UNKNOWN
tPU
50%
DATA VALID
tPD
50%
Note 4. Addresses valid prior to or coincident with S transition low.
5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 6)
VIH
OE
VIL
t CR
ta (OE)
(Note 5)
tdis(OE)
(Note 5) ten(OE)
DQ1~4
VOH
VOL
W=H
S=L
UNKNOWN
DATA VALID
Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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