M41T256YMT7 查看數據表（PDF） - STMicroelectronics
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M41T256YMT7 Datasheet PDF : 27 Pages
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M41T256Y
Figure 9. Bus Timing Requirements Sequence
SDA
tBUF
SCL
P
tHD:STA
tR
tF
tHIGH
S
tLOW
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can start
1.3
µs
tF
SDA and SCL Fall Time
300
ns
tHD:DAT
Data Hold Time
0
µs
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tR
SDA and SCL Rise Time
300
ns
tSU:DAT(2)
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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