72SD3232BRPFK 查看數據表（PDF） - MAXWELL TECHNOLOGIES
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72SD3232BRPFK Datasheet PDF : 41 Pages
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1 Gbit(8-Meg X 32-Bit X 4-Banks) SDRAM
72SD3232B
DQM1 - DQM4 Truth Table
COMMAND
(DQ248 to DQ31) write enable/output enable
(DQ248 to DQ31) write inhibit/output disable
(DQ16 to DQ24) write enable/output enable
(DQ16 to DQ24) write inhibit/output disable
(DQ8 to DQ15) write enable/output enable
(DQ8 to DQ15) write inhibit/output disable
(DQ0 to DQ7) write enable/output enable
(DQ0 to DQ7) write inhibit/output disable
SYMBOL
ENB4
MASK4
ENB3
MASK3
ENB2
MASK2
ENB1
MASK1
CKE =
N-1
H
H
H
H
H
H
H
H
CKE =
N
x
x
x
x
x
x
x
x
DQM4
H
L
x
x
x
x
x
x
DQM3
x
x
H
L
x
x
x
x
DQM2
x
x
x
x
H
L
x
x
DQM1
x
x
x
x
x
x
H
L
Note: H: VIH L: VIL x VIH or VIL
Write: IDID is Needed
Read: IDOD is Needed
The SDRAM can mask input/output data by means of DQM1- DQM4.
During reading, the output buffer is set to Low-Z by setting DQM1 - DQM4 to Low, enabling data output. On
the other hand, when DQM1 - DQM4 are set High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQM1 - DQM4 to Low. When DQM1 - DQM4 is set to High, the
previous data is held ( the new data is not written). Desired data can be masked during burst read or burst
write by setting DQM1 - DQM4. For more details, refer to the DQM1 - DQM4 control section of the SDRAM
operating instructions.
06.11.08 Rev 1
All data sheets are subject to change without notice 10
©2008 Maxwell Technologies
All rights reserved.
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