ADM6318CW45ARJZ 查看數據表（PDF） - Analog Devices

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ADM6318CW45ARJZ

Supervisory Circuits with Watchdog and Manual Reset in 5-Lead SOT-23

Analog Devices 

Data Sheet ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/ADM6321/ADM6322

CIRCUIT DESCRIPTION

The ADM6316/ADM6317/ADM6318/ADM6319/ADM6320/

ADM6321/ADM6322 provide microprocessor supply voltage

supervision by controlling the reset input of the microprocessor.

Code execution errors are avoided during power-up, power-down,

and brownout conditions by asserting a reset signal when the

supply voltage is below a preset threshold and by allowing supply

voltage stabilization with a fixed timeout reset pulse after the

supply voltage rises above the threshold. In addition, problems

with microprocessor code execution can be monitored and

corrected with a watchdog timer (ADM6316/ADM6317/

ADM6318/ADM6320/ADM6321). If the user detects a problem

with the system’s operation, a manual reset input is available

(ADM6316/ADM6317/ADM6319/ADM6320/ADM6322) to reset

the microprocessor, for example, by means of an external push

button.

RESET OUTPUT

The ADM6316 features an active low push-pull reset output,

while the ADM6317/ADM6321/ADM6322 have active high

push-pull reset outputs. The ADM6318/ADM6319 feature dual

active low and active high push-pull reset outputs. For active

low and active high outputs, the reset signal is guaranteed to be

logic low and logic high, respectively, for VCC down to 1 V.

The reset output is asserted when VCC is below the reset thresh-

old (VTH), when MR is driven low, or when WDI is not serviced

within the watchdog timeout period (tWD). Reset remains asserted

for the duration of the reset active timeout period (tRP) after VCC

rises above the reset threshold, after MR transitions from low to

high, or after the watchdog timer times out. Figure 17 illustrates

the behavior of the reset outputs.

VCC

VCC

1V

0V

VCC

RESET

0V

VTH

tRP

VTH

tRD

VCC

RESET

1V

tRP

tRD

0V

Figure 17. Reset Timing Diagram

OPEN-DRAIN RESET OUTPUT

The ADM6320/ADM6321/ADM6322 have an active low, open-

drain reset output. This output structure requires an external

pull-up resistor to connect the reset output to a voltage rail no

higher than 6 V. The resistor must comply with the micro-

processor’s logic low and logic high voltage level requirements

while supplying input current and leakage paths on the RESET

line. A 10 kΩ resistor is adequate in most situations.

MANUAL RESET INPUT

The ADM6316/ADM6317/ADM6319/ADM6320/ADM6322

feature a manual reset input (MR), which when driven low, asserts

the reset output. When MR transitions from low to high, reset

remains asserted for the duration of the reset active timeout

period before deasserting. The MR input has a 52 kΩ, internal

pull-up so that the input is always high when unconnected. An

external push-button switch can be connected between MR and

ground so that the user can generate a reset. Debounce circuitry

for this purpose is integrated on chip. Noise immunity is provided

on the MR input, and fast, negative going transients of up to 100

ns (typical) are ignored. A 0.1 μF capacitor between MR and

ground provides additional noise immunity.

WATCHDOG INPUT

The ADM6316/ADM6317/ADM6318/ADM6320/ADM6321

feature a watchdog timer that monitors microprocessor activity.

A timer circuit is cleared with every low-to-high or high-to-low

logic transition on the watchdog input pin (WDI), which detects

pulses as short as 50 ns. If the timer counts through the preset

watchdog timeout period (tWD), reset is asserted. The micro-

processor is required to toggle the WDI pin to avoid being reset.

Failure of the microprocessor to toggle WDI within the timeout

period, therefore, indicates a code execution error, and the reset

pulse generated restarts the microprocessor in a known state.

As well as logic transitions on WDI, the watchdog timer is also

cleared by a reset assertion due to an undervoltage condition on

VCC or due to MR being pulled low. When reset is asserted, the

watchdog timer is cleared and does not begin counting again until

reset deasserts. The watchdog timer can be disabled by leaving

WDI floating or by three-stating the WDI driver.

VCC VCC

1V

0V

VCC

RESET

0V

VCC

WDI

0V

VTH

tRP

tWD

tRP

Figure 18. Watchdog Timing Diagram

Rev. H | Page 9 of 14

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