ADBF539WBBCZ4 查看數據表（PDF） - Analog Devices

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ADBF539WBBCZ4

Blackfin Embedded Processor

Analog Devices 

GENERAL DESCRIPTION

The ADSP-BF539/ADSP-BF539F processors are members of

the Blackfin® family of products, incorporating the Analog

Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin

processors combine a dual-MAC, state-of-the-art signal pro-

cessing engine, the advantages of a clean, orthogonal RISC-like

microprocessor instruction set, and single-instruction, multi-

ple-data (SIMD) multimedia capabilities into a single

instruction set architecture.

The ADSP-BF539/ADSP-BF539F processors are completely

code compatible with other Blackfin processors, differing only

with respect to performance, peripherals, and on-chip memory.

These features are shown in Table 1.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like program-

mability, multimedia support, and leading edge signal

processing in one integrated package.

Table 1. Processor Features

Feature

SPORTs

UARTs

SPI

TWI

CAN

MXVR

PPI

Internal 8M bit

Parallel Flash

Instruction

SRAM/Cache

Instruction SRAM

Data SRAM/Cache

Data SRAM

Scratchpad

Maximum

Frequency

Package Option

ADSP-BF539

4

3

3

2

1

1

1

—

16K bytes

64K bytes

32K bytes

32K bytes

4K bytes

533 MHz

1066 MMACS

BC-316

ADSP-BF539F8

4

3

3

2

1

1

1

1

16K bytes

64K bytes

32K bytes

32K bytes

4K bytes

533 MHz

1066 MMACS

BC-316

LOW POWER ARCHITECTURE

Blackfin processors provide world class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature dynamic

power management, the ability to vary both the voltage and fre-

quency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

substantial reduction in power consumption, compared with

simply varying the frequency of operation. This translates into

longer battery life and lower heat dissipation.

ADSP-BF539/ADSP-BF539F

SYSTEM INTEGRATION

The ADSP-BF539/ADSP-BF539F processors are highly inte-

grated system-on-a-chip solutions for the next generation of

industrial and automotive applications including audio and

video signal processing. By combining advanced memory con-

figurations, such as on-chip flash memory, with industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a MOST Network Media Transceiver (MXVR), three

UART ports, three SPI ports, four serial ports (SPORT), one

CAN interface, two 2-wire interfaces (TWI), four general-pur-

pose timers (three with PWM capability), a real-time clock, a

watchdog timer, a parallel peripheral interface, general-purpose

I/O, and general-purpose flag pins.

ADSP-BF539/ADSP-BF539F PROCESSOR

PERIPHERALS

The ADSP-BF539/ADSP-BF539F processors contain a rich set

of peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see Figure 1 on Page 1).

The general-purpose peripherals include functions such as

UART, timers with PWM (pulse-width modulation) and pulse

measurement capability, general-purpose flag I/O pins, a real-

time clock, and a watchdog timer. This set of functions satisfies

a wide variety of typical system support needs and is augmented

by the system expansion capabilities of the device. In addition to

these general-purpose peripherals, the processors contain high

speed serial and parallel ports for interfacing to a variety of

audio, video, and modem codec functions. An MXVR trans-

ceiver transmits and receives audio and video data and control

information on a MOST automotive multimedia network. A

CAN 2.0B controller is provided for automotive control net-

works. An interrupt controller manages interrupts from the on-

chip peripherals or external sources. And power management

control functions tailor the performance and power characteris-

tics of the processor and system to many application scenarios.

All of the peripherals, GPIO, CAN, TWI, real-time clock, and

timers, are supported by a flexible DMA structure. There are

also four separate memory DMA channels dedicated to data

transfers between the processor’s various memory spaces,

including external SDRAM and asynchronous memory. Multi-

ple on-chip buses running at up to 133 MHz provide enough

bandwidth to keep the processor core running along with activ-

ity on all of the on-chip and external peripherals.

The ADSP-BF539/ADSP-BF539F processors include an on-chip

voltage regulator in support of the processor’s dynamic power

management capability. The voltage regulator provides a range

of core voltage levels from V . DDEXT The voltage regulator can be

bypassed at the user's discretion.

Rev. F | Page 3 of 60 | October 2013

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