ADBF539WBBCZ4 查看數據表（PDF） - Analog Devices

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ADBF539WBBCZ4

Blackfin Embedded Processor

Analog Devices 

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The ADSP-BF539/ADSP-BF539F processor’s event controller

consists of two stages, the core event controller (CEC) and the

system interrupt controller (SIC). The core event controller

works with the system interrupt controller to prioritize and con-

trol all system events. Conceptually, interrupts from the

peripherals enter into the SIC and are then routed directly into

the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the processor’s peripherals. Table 2 describes the inputs

to the CEC, identifies their names in the event vector table

(EVT), and lists their priorities.

System Interrupt Controller (SIC)

The system interrupt controller (SIC) provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF539/ADSP-BF539F processors provide a

default mapping, the user can alter the mappings and priorities

of interrupt events by writing the appropriate values into the

interrupt assignment registers (SIC_IARx). Table 3 describes

the inputs into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF539/ADSP-BF539F processors provide the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 32 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and is

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it can also be written to clear (cancel) latched events. This

ADSP-BF539/ADSP-BF539F

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event,

preventing the processor from servicing the event even

though the event can be latched in the ILAT register. This

register can be read or written while in supervisor mode.

General-purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates whether the event is currently

active or nested at some level. This register is updated auto-

matically by the controller but can be read while in

supervisor mode.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 8.

• SIC interrupt mask registers (SIC_IMASKx) – These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in these registers, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in these registers masks

the peripheral event, preventing the processor from servic-

ing the event.

• SIC interrupt status registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates that the

peripheral is asserting the interrupt, and a cleared bit indi-

cates that the peripheral is not asserting the event.

• SIC interrupt wake-up enable registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled or in sleep mode when the event is generated.

(For more information, see Dynamic Power Management

on Page 13.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the

Rev. F | Page 7 of 60 | October 2013

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