ADBF539WBBCZ4 查看數據表（PDF） - Analog Devices

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ADBF539WBBCZ4

Blackfin Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

general-purpose interrupt to the IPEND output asserted is three

core clock cycles; however, the latency can be much higher,

depending on the activity within and the state of the processor.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Event Class

Emulation/Test Control

Reset

Nonmaskable Interrupt

Exception

Reserved

Hardware Error

Core Timer

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

EVT Entry

EMU

RST

NMI

EVX

—

IVHW

IVTMR

IVG7

IVG8

IVG9

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

Table 3. System and Core Event Mapping

Event Source

PLL Wake-Up Interrupt

DMA Controller 0 Error

DMA Controller 1 Error

PPI Error Interrupt

SPORT0 Error Interrupt

SPORT1 Error Interrupt

SPORT2 Error Interrupt

SPORT3 Error Interrupt

MXVR Synchronous Data Interrupt

SPI0 Error Interrupt

SPI1 Error Interrupt

SPI2 Error Interrupt

UART0 Error Interrupt

UART1 Error Interrupt

UART2 Error Interrupt

CAN Error Interrupt

Real-Time Clock Interrupt

DMA0 Interrupt (PPI)

DMA1 Interrupt (SPORT0 Rx)

DMA2 Interrupt (SPORT0 Tx)

Core

Event Name

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG8

IVG8

IVG9

IVG9

Table 3. System and Core Event Mapping (Continued)

Event Source

DMA3 Interrupt (SPORT1 Rx)

DMA4 Interrupt (SPORT1 Tx)

DMA8 Interrupt (SPORT2 Rx)

DMA9 Interrupt (SPORT2 Tx)

DMA10 Interrupt (SPORT3 Rx)

DMA11 Interrupt (SPORT3 Tx)

DMA5 Interrupt (SPI0)

DMA14 Interrupt (SPI1)

DMA15 Interrupt (SPI2)

DMA6 Interrupt (UART0 Rx)

DMA7 Interrupt (UART0 Tx)

DMA16 Interrupt (UART1 Rx)

DMA17 Interrupt (UART1 Tx)

DMA18 Interrupt (UART2 Rx)

DMA19 Interrupt (UART2 Tx)

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

TWI1 Interrupt

CAN Receive Interrupt

CAN Transmit Interrupt

MXVR Status Interrupt

MXVR Control Message Interrupt

MXVR Asynchronous Packet Interrupt

Programmable Flags Interrupts

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

Core

Event Name

IVG9

IVG9

IVG9

IVG9

IVG9

IVG9

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG12

IVG13

IVG13

IVG13

IVG13

IVG13

DMA CONTROLLERS

The processors have multiple, independent DMA controllers

that support automated data transfers with minimal overhead

for the processor core. DMA transfers can occur between the

ADSP-BF539/ADSP-BF539F processor internal memories and

any of its DMA capable peripherals. Additionally, DMA trans-

fers can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interfaces, including the SDRAM controller and the

asynchronous memory controller. DMA capable peripherals

include the SPORTs, SPI ports, UARTs, and PPI. Each individ-

ual DMA capable peripheral has at least one dedicated DMA

channel. In addition, the MXVR peripheral has its own dedi-

cated DMA controller, which supports its own unique set of

operating modes.

Rev. F | Page 8 of 60 | October 2013

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