ADSP-BF527C(RevPrC) 查看數據表（PDF） - Analog Devices

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ADSP-BF527C
(Rev.:RevPrC)

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C

Bypass Mode

The bypass mode routes analog line inputs directly to the analog

line and headphone outputs as shown in Figure 16.

MICIN

12.5 K:

-

VMID

+

FROM

LINE

INPUTS

FROM

DAC

SIDETONE (OFF)

BYPASS (ON)

DACSEL (OFF)

-

VMID

+

LINEOUT

Figure 16. Signal Routing in Bypass Mode

Bypass mode is selected under software control using the

BYPASS bit as shown in Table 8. In true bypass mode, the out-

put from the DAC (DACSEL) and (SIDETONE) should be de-

selected from the line output block. However this can also be

used to sum the DAC output, line inputs together and micro-

phone inputs. The analog line input and headphone output

volume controls and mutes are still operational in bypass mode.

The 0 dB gain setting is recommended for the line input volume

control to avoid distortion. The maximum signal at any point in

the bypass path must be no greater than 1.0 V(rms) at AVDD =

3.3 V. This level tracks directly with AVDD. This means that if

the DAC is producing a 1 V(rms) signal, and it is being summed

with a 1 V(rms) line BYPASS signal, the resulting LINEOUT

signal will be clipped.

Table 8. Bypass Mode Software Control

Register

Address

000 0100

Bit Label

3 BYPASS

Default

1

Description

Bypass Switch (analog)

1 = Enable Bypass

0 = Disable Bypass

-

VMID +

HPOUT

Rev. PrC | Page 13 of 44 | June 2008

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